#========================================================
#script for Design Compiler
# Language  : TCL
# Usage     :
#           1) make sure the lib in the current directory
#           2) if you have the file .synopsys_dc.setup,
#              set synopsys_dc_setup_file 1,
#              if not, set synopsys_dc_setup_file 0
#           3) change Step 3 : Variables to what you want
#              Especially : top module name, clock name,
#              reset name, all files name, and period
#           4) typing dc_shell-t -f run_72.tcl | tee -i run.log
#           
#========================================================

set synopsys_dc_setup_file 0
#-----------------------------------------------------
# Step 1 :
# Setting Up path and library
# If you have edited the file .synopsys_dc.setup,
# then you can skip over this step
#-----------------------------------------------------
if { $synopsys_dc_setup_file == 0} {
set search_path { \
../lib/TSMC90 \
../source \
../script \
}
set target_library  {fast.db} 
#set target_library  {CSM35OS142_typ.db};               
# if you want use fast library,change to fast.db
#set link_library  [list {*} ram_interp_fast_syn.db ram_458_fast_syn.db fast.db]
set link_library  "* $target_library"
}
#set symbol_library  {csm18ic.sdb csm18io.sdb}
#set synthetic_library  {dw_foundation.sldb};   
# Design Ware
set command_log_file   "command.log"

#-----------------------------------------------------
# Step 2 :
# Compile Swithes
#-----------------------------------------------------
#set verilogout_no_tri 				 true ;       
# if inout used, tri net will be used
set test_default_scan_style          multiplexed_flip_flop
set link_force_case                  case_insensitive
define_name_rules VLSI_NET -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type net -max_length 256
define_name_rules VLSI_CELL -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type cell -max_length 256
define_name_rules VLSI_PORT -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type port -max_length 256
define_name_rules TAN_RULE -allowed "a-zA-Z0-9_" -first_restricted "0-9_\[]" -max_length 256 -map {{{"*cell*", "mycell"}, {"*-return", "myreturn"}}};
set hdlin_check_no_latch "true"
set hdlin_merge_nested_conditional_statements "true"

#-----------------------------------------------------
# Step 3 :
# Define Variables
#-----------------------------------------------------
source ../script/files.tcl;                                   
source ../sdc/define.sdc;

set area_desired 0;
set wire_load_model "tsmc090_wl10";              
# Model of the intra net
set output_load "fast/NAND2BX1/AN" ;                
# model of the output_load

set synthesis_reports  {../report};   
#name of report directory
sh  mkdir -p $synthesis_reports;
set timing_report       "$synthesis_reports/$active_design\_timing.rpt"
set timing_max20_report "$synthesis_reports/$active_design\_timing_max20.rpt"
set area_report         "$synthesis_reports/$active_design\_area.rpt"
set references_report   "$synthesis_reports/$active_design\_references.rpt"
set cell_report         "$synthesis_reports/$active_design\_cell.rpt"
set constraint_report   "$synthesis_reports/$active_design\_constraint.rpt"
set power_report        "$synthesis_reports/$active_design\_power.rpt"
set check_syntax_report "$synthesis_reports/$active_design\_check_design.rpt"
set qor_report          "$synthesis_reports/$active_design\_qor.rpt"

set synthesis_netlist  {../result}; 
#name of outfile directory
sh  mkdir -p $synthesis_netlist;
set out_netlist         "$synthesis_netlist/$active_design.v";
set out_db              "$synthesis_netlist/$active_design.db";
set out_sdf             "$synthesis_netlist/$active_design.sdf";
set out_sdc             "$synthesis_netlist/$active_design.sdc";


#-----------------------------------------------------
# Step 4 :
# Read design to DC Memory
#-----------------------------------------------------
#no parameter
#foreach active_files $files {	
#                             read_verilog $active_files}
#current_design $active_design
#link
#uniquify

#parameter
foreach active_files $files {analyze -format verilog $active_files}
elaborate $active_design
uniquify


#-----------------------------------------------------
# Step 5 :
# Constraint 
#-----------------------------------------------------
source ../sdc/clock.sdc;
source ../sdc/io.sdc;

#-----Net load------
set_wire_load_model -name $wire_load_model
set_wire_load_mode top

#-----clock------
set_clock_uncertainty -setup $clk_uncertainty_setup [get_clocks $clock_name]
set_clock_latency $clk_latency [get_clocks $clock_name]
set_dont_touch_network [get_clocks $clock_name]
set_dont_touch_network [get_ports $reset_name]
set_ideal_network [get_ports $reset_name]

#-----drive------
#set_driving_cell -lib_cell xr02d2 -pin A1 -library CSM35OS142_typ  [all_inputs]
set_driving_cell -lib_cell NAND2BX1 -pin Y [all_inputs]
set_drive 0 [get_ports $clock_name]
set_drive 0 [get_ports $reset_name]

#-----Output load------
set_load [load_of $output_load] [all_outputs]

#----- Area ------
#set_max_area $area_desired

#----- insert buffer replace assign ------
set_fix_multiple_port_nets -all -buffer_constants


#-----------------------------------------------------
# Step 6 :
# Compile 
# Also can use compile_ultra
#-----------------------------------------------------
compile -map_effort medium -boundary_optimization 
#-area_effort high
#compile -incremental_mapping


#-----------------------------------------------------
# Step 7 :
# Reports (Timing, Area ...)
#-----------------------------------------------------
remove_unconnected_ports [get_cells -hier {*}]
change_names -hierarchy -rules TAN_RULE
report_timing -delay max -max_paths 100 > $timing_report
report_timing -delay max -path end -max_path 80 > $timing_max20_report
#report_area -hierarchy > $area_report
report_area -hierarchy > $area_report
#report_reference -hierarchy > $references_report
report_reference -hierarchy > $references_report
report_cell [get_cells -hier *] > $cell_report
report_constraint -all_violators -verbose > $constraint_report
report_power -analysis_effort high -verbose > $power_report
check_design > $check_syntax_report
report_qor > $qor_report


#-----------------------------------------------------
# Step 8 :
# Write Files (netlist out)
#-----------------------------------------------------
change_names -rule verilog -hier
write -format verilog -hierarchy -output $out_netlist
write -format ddc -hierarchy -output $out_db
write_sdf  $out_sdf
write_sdc  $out_sdc
exit
#----------------------end-------------------
